Rockchip RK3399 is a low power, high performance processor for computing, personal mobile internet devices and other smart device applications. Based on Big.Little architecture, it integrates dual-core Cortex-A72and quad-core Cortex-A53 with separate NEON coprocessor.It also integrates Mali T860 MP4 GPU.

Overview

RK3399 have very good Linux support including U-Boot, kernel, graphics, video decoder and encoder.

RK3399 SoC Feature

• CPU
  • Dual-core ARM Cortex-A72 MPCore processor and Quad-core ARM Cortex-A53 MPCore processor, both are high-performance, low-power and cached application processor.
  • Two CPU clusters. Big cluster with dual-core Cortex-A72 is optimized for high-performance and little cluster with quad-core Cortex-A53 is optimized for low power.
  • Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerating media and signal processing
  • CCI500 ensures the memory coherency between the two clusters
  • Each Cortex-A72 integrates48KB L1 instruction cache and 32KB L1 data cache with 4-way set associative. Each Cortex A53 integrates 32KB L1 instruction cache and 32kB L1 data cache separately with 4-way set associative
  • 1MB unified L2 Cache for Big cluster, 512KB unified L2 Cache for Little cluster
  • Trustzone technology support
• GPU
  • ARM Mali-T860MP4 GPU, support OpenGL ES1.1/2.0/3.0, OpenCL1.2, DirectX11.1 etc
  • Embedded 4 shader cores with shared hierarchical tiler
• Memory
  • Dynamic Memory Interface (DDR3/DDR3L/LPDDR3/LPDDR4)： Compatible with JEDEC standard DDR3-1866 /DDR3L-1866 /LPDDR3-1866 /LPDDR4 SDRAM. Support 2 channels, each channel is 16 or 32bits data width. Support up to 2 ranks (chip selects) for each channel; totally 4GB(max) address space. Maximum address space of one rank in a channel is also 4GB, which is software-configurable
  • eMMC Interface: ully compliant with JEDEC eMMC 5.1and eMMC 5.0 specification. Supports HS400, HS200, DDR50 and legacy operating modes.
  • SD/MMC Interface: There are 2 MMC interfaces which can be configured as SD/MMC or SDIO. Compatible with SD3.0, MMC ver4.51
• System Component
  • Timer: 14 on-chip 64bits Timers in SoC with interrupt-based operation for non-secure application. 12 on-chip 64bits Timers in SoC with interrupt-based operation for secure application
  • PWM: Four on-chip PWMs with interrupt-based operation
  • WatchDog: Three Watchdogs in SoC with 32 bits counter width
• Video
  • Real-time video decoder of MPEG-1, MPEG-2, MPEG-4,H.263, H.264, H.265, VC-1, VP9, VP8, MVC
  • H.264 10bit up to HP level 5.1 : 2160p@60fps (4096x2304)
  • VP9 : 2160p@60fps(4096x2304)
  • H.265/HEVC 10bit: 2160p@60fps(4096x2304)
  • MPEG-4 up to ASP level 5 : 1080p@60fps (1920x1088)
  • MPEG-2 up to MP: 1080p@60fps (1920x1088)
  • MPEG-1 up to MP: 1080p@60fps (1920x1088)
  • H.263: 576p@60fps (720x576)
  • VC-1 up to AP level 3: 1080p@30fps (1920x1088)
  • VP8: 1080p@60fps (1920x1088)
  • MVC: 1080p@60fps (1920x1088)
  • Support video encoder for H.264, MVC and VP8
• Display
  • Embedded two VOP, output from the following display interface: One or Two MIPI-DSI port, One eDP port, One DP port, One HDMI port
  • Support AFBC function co-operation with GPU
  • HDMI interface: Single Physical Layer PHY with support for HDMI 1.4 and 2.0 operation. Support HDCP 1.4/2.2
  • MIPI interface: Embedded 3 MIPI PHY, MIPI0 only for DSI, MIPI1 for DSI or CSI, MIPI2 only for CSI. Each port has 4 data lane, providing up to 6.0 Gbps data rate
  • eDP interface: Compliant with eDPTM Specification, version 1.3. Up to 4 physical lanes of 2.7/1.62 Gbps/lane
  • DisplayPort interface: Compliant with DisplayPort Specification, version 1.2. Compliant with HDCP2.2 (and back compatible with HDCP1.3). There is only one DisplayPort controller built-in RK3399 which is shared by 2 Type-C.
• Camera Interface and Image Processer
  • One or two MIPI-CSI input interface
  • two ISP (Image Sensor Processor) embed
  • Maximum input resolution of one ISP is 13M pixels
• TYPE-C
  • Embedded 2 Type-C PHY
  • Compliant with USB Type-C Specification, revision 1.1
  • Compliant with USB Power Delivery Specification, revision 2.0
  • Attach/detach detection and signaling as DFP, UFP and DRP
  • Plug orientation/cable twist detection
  • Support USB3.0 Type-C and DisplayPort 1.2 Alt Mode on USB Type-C. Two PMA TX-only lanes and two PMA half-duplex TX/RX lanes (can be configured as TX-only or RX-only)
  • Up to 5Gbps data rate for USB3.0
  • Up to 5.4Gbps(HBR2) data rate for DP1.2, can support 1/2/4 lane mode
• Audio
  • I2S/PCM: Three I2S/PCM in SoC. I2S0/I2S2 support up to 8 channels TX and 8 channels RX. I2S1 supports up to 2 channels TX and 2 channels RX. I2S2 is connected to HDMI and DisplayPort internally. I2S0 and I2S1 are exposed for peripherals
  • SPDIF: Support two 16-bit audio data store together in one 32-bit wide location. Support biphase format stereo audio data output. Support 16 to 31 bit audio data left or right justified in 32-bit wide sample data buffer. Support 16, 20, 24 bits audio data transfer in linear PCM mode
• Connectivity
  • SDIO interface: Compatible with SDIO 3.0 protocol
  • GMAC 10/100/1000M Ethernet Controller: Supports 10/100/1000-Mbps data transfer rates with the RGMII interfaces. Supports 10/100-Mbps data transfer rates with the RMII interfaces
  • SPI Controller: 6 on-chip SPI controller inside
  • Uart Controller: 5 on-chip uart controller inside
  • I2C controller: 9 on-chip I2C controller inside
  • USB Host2.0: Embedded 2 USB 2.0 Host interfaces.
  • USB OTG3.0: Embedded 2 USB OTG3.0 interfaces.
  • PCIe: One PCIe port Compatible with PCI Express Base Specification Revision 2.1
• Other
  • Temperature Sensor(TS-ADC): Embedded 2 channel TS-ADC
  • SAR-ADC (Successive Approximation Register): 6-channel single-ended 10-bit SAR analog-to-digital converter. Conversion speed range is up to 1MS/s sampling rate
  • eFuse: Two 1024bits(32x32) high-density electrical Fuse are integrated

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Devices